The present invention relates to a data processing arrangement and, more particularly, to a data processing arrangement for increasing the number of peripheral input/output devices that may be used with a microprocessor.
Commercially-available microprocessors may be used with a number of peripheral input/output devices. In one particular arrangement, a microprocessor is coupled with a plurality of peripheral input/output devices connected with each other in succession to form a serial daisy chain. This serial daisy chain establishes a priority sequence with the first device in the series having the highest priority and the last device in the series having the lowest priority. Each input/output device includes an input, an output connected directly to the input of the next device, and is capable of communicating with the microprocessor by means of a common interrupt line, control lines, and a common data bus. Whenever a particular input/output device requests service, for example, to apply data (e.g., vector data) to the microprocessor, the requesting device causes its associated output to drop from a first voltage level, for example, a high voltage level, to a second voltage level, for example, a low voltage level. Simultaneously therewith, the requesting device also drops the interrupt line from a high voltage level to a low voltage level. The low voltage level at the output of the requesting input/output device is coupled to the input of the next input/output device and caused to be propagated, or rippled, down through the remaining input/output devices in the series to cause the inputs thereof to go from high to low voltage levels. The propagation of the low voltage level along the daisy chain prevents the remaining devices in the series from requesting access to the microprocessor following the higher priority device requesting service and dropping the interrupt line.
The dropping of the interrupt line by the device requesting service is noted by the microprocessor whereupon an interrupt request/acknowledge cycle or sequence is initiated for producing control signals for controlling the application of vector data by the requesting input/output device to the microprocessor. These signals also establish a fixed time period of a duration sufficient to allow the input/output devices to settle out or stabilize, due to propagation delays, as a low voltage level from a requesting input/output device propagates or ripples down through the remaining input/output devices. At the termination of this fixed time period, vector data from the requesting input/output device is applied to the microprocessor via the common data bus thereby positively placing the device "under service" and allowing the microprocessor to execute an interrupt service routine associated with the particular input/output device. Upon completion of the interrupt service routine for the "under service" input/output device, the input/output device is reset by the microprocessor. This latter operation can be readily accomplished in a two-byte reset instruction of the microprocessor. More particularly, a first microprocessor op code is applied to the data bus and decoded by all of the "out of service" input/output devices to place their outputs at high voltage levels whereby the input of the "under service" device is established at a high voltage level. A second microprocessor op code applied to the data bus is then decoded by the "under service" input/output device to reset an internal interrupt structure of the input/output device thereby to allow a subsequent interrupt operation by the input/output device.
While the arrangement as described hereinabove operates in a generally satisfactory manner, the maximum number of peripheral input/output devices which can be used with the microprocessor tends to be quite small, for example, less than ten devices. Thus, if it is desired to use ten or more peripheral input/output devices with the microprocessor, it is generally necessary to make some modification or change in the arrangement as described hereinabove. One solution which has been proposed is to increase the fixed settling time period established by the microprocessor so as to accommodate the increased number of input/output devices and the increased propagation delays. This increase in the settling time period would normally be required to deal with the situation in which two or more input/output devices simultaneously request service by simultaneously dropping the interrupt line. If the settling time in this latter situation is not increased, it is possible for a low priority device dropping the interrupt line simultaneously with a higher priority device, especially a much higher priority device, to fail to establish its input at a low voltage level (due to propagation from the output of the higher priority device) during the settling time period. As a result, two sets of vector data will be placed on the data bus simultaneously by the two input/output devices, leading to a malfunction of the system software.
A disadvantage of the above proposed solution is that an increase in the duration of the settling time period of the microprocessor to accommodate an increased number of input/output devices and associated propagation delays requires either substantial modification of the internal software of the microprocessor or the addition of substantial amounts of hardware which alters internal operations of the microprocessor. These modifications can be accomplished only at the expense of sacrificing processing or computing power of the microprocessor, that is, performance, and militates against the purpose for which the microprocessor may have been selected in the first place. An additional problem in attempting to increase the number of input/output devices usable with the microprocessor as discussed hereinabove is that it is possible for a high priority input/output device seeking service after a lower priority device has been placed "under service" by the microprocessor to alter the input voltage level of the "under service" device so that it does not recognize and decode the second reset op code from the microprocessor. As a result, the internal interrupt structure of the "under service" input/output device fails to be reset and thereby prevents input/output devices of lower priority from initiating interrupt operations.